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OptiMOS? 5 25 V and 30 V?

Benchmark power density and energy efficiency in standby and full operation with OptiMOS? 5 power MOSFETs in 25 V and 30 V

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Overview

OptiMOS? 5 power MOSFETs in 25 V and 30 V enable the highest power density and energy efficiency, both in standby and full operation. The family is available in SuperSO8 5x6, PQFN 3.3x3.3, Source-Down PQFN 3.3x3.3, PQFN 2x2, and Power Block packages.

Key Features

  • Best-in-class RDS(on)
  • Benchmark switching performance
  • RoHS-compliant and halogen-free
  • Low gate charge
  • Highest efficiency

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About

New silicon technology for next-generation DC-DC applications

OptiMOS? 5 MOSFETs in 25 V and 30 V products are based on a new silicon technology, optimized to meet, and exceed the energy efficiency and power density requirements of the tightened, next-generation voltage regulation standards in DC-DC applications.

OptiMOS? 5 products address a broad range of voltage regulation applications in the computing industry, such as servers, datacom, and clients focusing on Intel¡¯s VR and IMVP platforms.

OptiMOS? 5 features best-in-class on-state resistance and benchmark switching performance that will optimize your designs and lower the system costs in general.

Industry's lowest RDS(on) for 25 V and 30 V

Infineon¡¯s new ISK024NE2LM5 and ISK036N03LM5 OptiMOS? 5 products in PQFN 2x2 packaging offers the best-in-class solution for efficiency in a small form factor, making it the perfect solution for applications such as wireless charging, load switches, and low-power DC-DC applications.

The small 4 mm? footprint, combined with outstanding electrical performance improves the form factor in end applications. These products are optimized for the highest performance and power density featuring industry¡¯s lowest?RDS(on) in the smallest PQFN 2x2 package.

Innovative package with superior thermal performance

The OptiMOS? 5 power MOSFETs ?25 V-30 V in PQFN 3.3x3.3 mm? and 5x6 mm? Source-Down packages are now available in a BSC (bottom-side cooling) and a DSC (dual-side cooling) variant, with two different footprints: a Corner-Gate- and a Center-Gate version, with the latter optimized explicitly for parallelization.

The Source-Down package concept enables the lowest RDS(on) per footprint area and outstanding thermal performance, giving significant potential for improvements on a system level, like BOM-cost reduction, easy thermal management with less active cooling required, improvement of power density, and efficiency.

Learn more about the Source-Down package

New silicon technology for next-generation DC-DC applications

OptiMOS? 5 MOSFETs in 25 V and 30 V products are based on a new silicon technology, optimized to meet, and exceed the energy efficiency and power density requirements of the tightened, next-generation voltage regulation standards in DC-DC applications.

OptiMOS? 5 products address a broad range of voltage regulation applications in the computing industry, such as servers, datacom, and clients focusing on Intel¡¯s VR and IMVP platforms.

OptiMOS? 5 features best-in-class on-state resistance and benchmark switching performance that will optimize your designs and lower the system costs in general.

Industry's lowest RDS(on) for 25 V and 30 V

Infineon¡¯s new ISK024NE2LM5 and ISK036N03LM5 OptiMOS? 5 products in PQFN 2x2 packaging offers the best-in-class solution for efficiency in a small form factor, making it the perfect solution for applications such as wireless charging, load switches, and low-power DC-DC applications.

The small 4 mm? footprint, combined with outstanding electrical performance improves the form factor in end applications. These products are optimized for the highest performance and power density featuring industry¡¯s lowest?RDS(on) in the smallest PQFN 2x2 package.

Innovative package with superior thermal performance

The OptiMOS? 5 power MOSFETs ?25 V-30 V in PQFN 3.3x3.3 mm? and 5x6 mm? Source-Down packages are now available in a BSC (bottom-side cooling) and a DSC (dual-side cooling) variant, with two different footprints: a Corner-Gate- and a Center-Gate version, with the latter optimized explicitly for parallelization.

The Source-Down package concept enables the lowest RDS(on) per footprint area and outstanding thermal performance, giving significant potential for improvements on a system level, like BOM-cost reduction, easy thermal management with less active cooling required, improvement of power density, and efficiency.

Learn more about the Source-Down package

Documents

Documents

Design resources

Developer community

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