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EZ-PD? CCG6DF dual-port and CCG6SF single-port USB-C PD controllers

EZ-PD? CCG6DF/CCG6SF USB-C Power Delivery solutions with integrated VBUS provider load switch

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Overview

EZ-PD? CCG6DF and EZ-PD? CCG6SF are USB-C and Power Delivery integrated controllers designed for PCs and notebooks, available in dual- and single-port configurations respectively. They are programmable solutions integrating a 64 KB flash and a 96 KB ROM, ensuring fail-safe boot up and supporting firmware upgrades. Both devices support dual role port (DRP) functionality and fully comply with the Power Delivery 3.0 specification.

Key Features

  • Supports USB-C PD 3.0
  • Supports USB3, USB4, Thunderbolt
  • Integrated digital & analog blocks
  • Up to 23 GPIOs, 4 SCBs
  • VBUS provider load switch (5 V/3 A)
  • Slew rate control turn-on on VBUS
  • USB PD 3.0 fast role swap support
  • Integrated high-voltage 20 V reg.
  • SBU pass through, USB analog mux
  • VBUS-to-CC/SBU short protection
  • VCONN FETs
  • VCONN overcurrent protection

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About

EZ-PD? CCG6DF/CCG6SF USB-C subsystem

The USB PD subsystems of EZ-PD? CCG6DF/CCG6SF are based on a USB PD physical layer and its supporting circuits. The USB PD physical layer consists of a transmitter and a receiver that communicate BMC-encoded data over the CC channel as per the PD 3.0 standard, using a half-duplex communication. Collision avoidance is employed by the physical layer (PHY) to minimize communication errors on the channel. Additionally, the USB PD block incorporates all necessary termination resistors (Rp and Rd) and their corresponding switches in accordance with the USB Type-C specification. The Rp resistor is implemented as a current source, while the Rd resistors on CC pins are essential for dead battery termination detection and charging.?

To comply with the latest USB PD 3.0 specification, both EZ-PD? CCG6DF and EZ-PD? CCG6SF include the fast role swap (FRS) feature. FRS enables externally powered docks and hubs to rapidly transition to bus power where their external power supply is disconnected.

EZ-PD? CCG6DF/CCG6SF MCU subsystem

EZ-PD? CCG6DF/CCG6SF incorporates an Arm? Cortex?-M0 CPU as part of its 32-bit MCU subsystem. This subsystem is specifically designed for efficient and low-power operation, utilizing extensive clock gating techniques. The CPU primarily utilizes 16-bit instructions and executes a subset of the Thumb-2 instruction set. Additionally, the CPU incorporates a hardware multiplier that produces a 32-bit result within a single cycle. It is equipped with an interrupt controller, known as the NVIC block, featuring 32 interrupt inputs. The processor also includes a wakeup interrupt controller (WIC) capable of waking the processor from Deep Sleep mode. The device also includes a 64 KB flash to store the temporary status of system variables and parameters and a 96 KB ROM containing the firmware necessary to implement the PD functionality and boot and configuration routines.

Why choose EZ-PD? CCG6DF/CCG6SF?

EZ-PD? CCG6DF/SF integrates various features on a single chip, including a VBUS provider path load switch controller, USB authentication support, VBUS-to-CC short protection, VBUS-to-SBU short protection, 20 V-VBUS regulator, high-voltage NFET gate drivers for VBUS consumer path, SBU pass-through, and USB HS mux. The device is a USB PD 3.0-compliant fully programmable solution approved for Thunderbolt applications that supports the DRP functionality.

EZ-PD? CCG6DF/CCG6SF USB-C subsystem

The USB PD subsystems of EZ-PD? CCG6DF/CCG6SF are based on a USB PD physical layer and its supporting circuits. The USB PD physical layer consists of a transmitter and a receiver that communicate BMC-encoded data over the CC channel as per the PD 3.0 standard, using a half-duplex communication. Collision avoidance is employed by the physical layer (PHY) to minimize communication errors on the channel. Additionally, the USB PD block incorporates all necessary termination resistors (Rp and Rd) and their corresponding switches in accordance with the USB Type-C specification. The Rp resistor is implemented as a current source, while the Rd resistors on CC pins are essential for dead battery termination detection and charging.?

To comply with the latest USB PD 3.0 specification, both EZ-PD? CCG6DF and EZ-PD? CCG6SF include the fast role swap (FRS) feature. FRS enables externally powered docks and hubs to rapidly transition to bus power where their external power supply is disconnected.

EZ-PD? CCG6DF/CCG6SF MCU subsystem

EZ-PD? CCG6DF/CCG6SF incorporates an Arm? Cortex?-M0 CPU as part of its 32-bit MCU subsystem. This subsystem is specifically designed for efficient and low-power operation, utilizing extensive clock gating techniques. The CPU primarily utilizes 16-bit instructions and executes a subset of the Thumb-2 instruction set. Additionally, the CPU incorporates a hardware multiplier that produces a 32-bit result within a single cycle. It is equipped with an interrupt controller, known as the NVIC block, featuring 32 interrupt inputs. The processor also includes a wakeup interrupt controller (WIC) capable of waking the processor from Deep Sleep mode. The device also includes a 64 KB flash to store the temporary status of system variables and parameters and a 96 KB ROM containing the firmware necessary to implement the PD functionality and boot and configuration routines.

Why choose EZ-PD? CCG6DF/CCG6SF?

EZ-PD? CCG6DF/SF integrates various features on a single chip, including a VBUS provider path load switch controller, USB authentication support, VBUS-to-CC short protection, VBUS-to-SBU short protection, 20 V-VBUS regulator, high-voltage NFET gate drivers for VBUS consumer path, SBU pass-through, and USB HS mux. The device is a USB PD 3.0-compliant fully programmable solution approved for Thunderbolt applications that supports the DRP functionality.

Documents

Documents

Design resources

Developer community

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