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Synchronous SRAM

High-speed static RAM memory technology architecture with synchronous operation for improved data throughput.

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About

Infineon’s sync SRAM memory family
  • Standard sync SRAMs: Designed for cache applications, with a 2-bit burst counter supporting cache line sizes of four. Available in densities from 2 Mbit to 72 Mbit.
  • No Bus Latency (NoBL?) sync SRAMs: Also known as Zero bus turn-around (ZBT) SRAMs, these eliminate idle cycles during bus transitions. Two versions are available: Flow-through and pipelined. Densities range from 2 Mbit to 144 Mbit.
  • DDR-II/II+/II+ Xtreme sync SRAMs: Featuring dual data rate (DDR) I/Os, suitable for read-intensive functions in networking/communication applications.
  • QDR-II/II+/II+ Xtreme sync SRAMs: Similar to DDR but featuring quad data rate (QDR) I/Os, ideal for low-latency network applications, with separate read and write buses. Densities range from 18 Mbit to 144 Mbit.
  • QDR-IV sync SRAMs: High-performance memory with two independent bidirectional data ports, maximizing random transactions per second. Available in 72 Mbit and 144 Mbit densities, suitable for high-speed networking applications.
  • Infineon's sync SRAMs portfolio caters to various performance, latency, and density requirements, enabling efficient memory solutions for a wide range of networking applications.
SRAM memory key features
  • Highest RTR - Industry-leading Random Transaction Rate of 2132 MT/s.?
  • QDR?-IV SRAMs are capable of operating in burst-of-two or banked burst-of-two modes, which deliver the fastest clock speeds and highest RTR of all QDR? SRAMs and also higher than competing RLDRAMs and DDR3 DRAMs.
  • High reliability - On-chip Error correction code (ECC) to provide the lowest soft error rate? of <0.1 FIT/Mbit
  • Improved Signal Integrity - The On-Die-Termination (ODT) feature in the DDR-II+ family of devices improves the signal quality at high frequencies (greater than 300 MHz)
Synchronous SRAM with ECC highlights

Infineon's synchronous SRAMs with ECC are the only high-density standard sync and NoBL? SRAMs in the market to be offered with the reliability of on-chip error detection and correction. With ECC to detect and correct single-bit errors, Infineon's synchronous SRAMs offer a FIT rate of <0.01 FIT/Mb that is 1,000x lower than a standard SRAM without ECC and are availabe in Industry-standard, RoHS-compliant packages.

Synchronous SRAM with ECC
About Dual data rate (DDR) sync SRAMs

DDR SRAMs are similar to the legacy synchronous burst SRAM products but with double data rate I/Os. Like the synchronous burst SRAMs, they are used for read-intensive functions such as packet lookup and packet classification in networking/communication applications. DDR SRAMs have a maximum clock speed of 550 MHz with a read latency of 1 cycle and are available in an industry-standard 165-ball BGA.

Dual data rate (DDR) sync SRAMs
QDR?-IV solution provides fast random memory access

Quadruple data rate (QDR?) SRAMs are similar to NoBL SRAMs but with architectural enhancements such as double data rate I/Os and dedicated read/write ports. QDR? SRAMs are used in networking applications where reads and writes are balanced such as packet buffer, statistics counters, flow state, and scheduling. QDR? SRAMs operate at a maximum speed of 1066 MHz with a read latency of 1 cycle and are available in an industry standard 165-ball BGA.

Quad data rate (QDR?) sync SRAMs
Random transaction rate (RTR)

Random transaction rate (RTR) is the number of fully random read or write transactions a memory can perform every second. It is measured in MT/s, or mega transactions per second. RTR is a critical metric in high-performance computing, general-purpose servers, and image-processing applications., where memory access is unpredictable.

The QDR consortium-defined quadruple data rate (QDR?) SRAM products are geared primarily to the networking and communication market. QDR? SRAMs allow access to any two memory locations on every clock cycle, and performance never depends on which memory location was accessed in the previous clock cycle. Hence, with QDR? SRAM, RTR is guaranteed.

QDR?-IV SRAMs are capable of operating in burst-of-two or banked burst-of-two modes, which deliver the fastest clock speeds and highest RTR of all QDR? SRAMs and also higher than competing RLDRAMs and DDR3 DRAMs.

Infineon's QDR?-IV SRAMs provide RTRs up to 2132 MT/s.

Infineon’s sync SRAM memory family
  • Standard sync SRAMs: Designed for cache applications, with a 2-bit burst counter supporting cache line sizes of four. Available in densities from 2 Mbit to 72 Mbit.
  • No Bus Latency (NoBL?) sync SRAMs: Also known as Zero bus turn-around (ZBT) SRAMs, these eliminate idle cycles during bus transitions. Two versions are available: Flow-through and pipelined. Densities range from 2 Mbit to 144 Mbit.
  • DDR-II/II+/II+ Xtreme sync SRAMs: Featuring dual data rate (DDR) I/Os, suitable for read-intensive functions in networking/communication applications.
  • QDR-II/II+/II+ Xtreme sync SRAMs: Similar to DDR but featuring quad data rate (QDR) I/Os, ideal for low-latency network applications, with separate read and write buses. Densities range from 18 Mbit to 144 Mbit.
  • QDR-IV sync SRAMs: High-performance memory with two independent bidirectional data ports, maximizing random transactions per second. Available in 72 Mbit and 144 Mbit densities, suitable for high-speed networking applications.
  • Infineon's sync SRAMs portfolio caters to various performance, latency, and density requirements, enabling efficient memory solutions for a wide range of networking applications.

SRAM memory key features
  • Highest RTR - Industry-leading Random Transaction Rate of 2132 MT/s.?
  • QDR?-IV SRAMs are capable of operating in burst-of-two or banked burst-of-two modes, which deliver the fastest clock speeds and highest RTR of all QDR? SRAMs and also higher than competing RLDRAMs and DDR3 DRAMs.
  • High reliability - On-chip Error correction code (ECC) to provide the lowest soft error rate? of <0.1 FIT/Mbit
  • Improved Signal Integrity - The On-Die-Termination (ODT) feature in the DDR-II+ family of devices improves the signal quality at high frequencies (greater than 300 MHz)

Synchronous SRAM with ECC highlights

Infineon's synchronous SRAMs with ECC are the only high-density standard sync and NoBL? SRAMs in the market to be offered with the reliability of on-chip error detection and correction. With ECC to detect and correct single-bit errors, Infineon's synchronous SRAMs offer a FIT rate of <0.01 FIT/Mb that is 1,000x lower than a standard SRAM without ECC and are availabe in Industry-standard, RoHS-compliant packages.

Synchronous SRAM with ECC

About Dual data rate (DDR) sync SRAMs

DDR SRAMs are similar to the legacy synchronous burst SRAM products but with double data rate I/Os. Like the synchronous burst SRAMs, they are used for read-intensive functions such as packet lookup and packet classification in networking/communication applications. DDR SRAMs have a maximum clock speed of 550 MHz with a read latency of 1 cycle and are available in an industry-standard 165-ball BGA.

Dual data rate (DDR) sync SRAMs

QDR?-IV solution provides fast random memory access

Quadruple data rate (QDR?) SRAMs are similar to NoBL SRAMs but with architectural enhancements such as double data rate I/Os and dedicated read/write ports. QDR? SRAMs are used in networking applications where reads and writes are balanced such as packet buffer, statistics counters, flow state, and scheduling. QDR? SRAMs operate at a maximum speed of 1066 MHz with a read latency of 1 cycle and are available in an industry standard 165-ball BGA.

Quad data rate (QDR?) sync SRAMs

Random transaction rate (RTR)

Random transaction rate (RTR) is the number of fully random read or write transactions a memory can perform every second. It is measured in MT/s, or mega transactions per second. RTR is a critical metric in high-performance computing, general-purpose servers, and image-processing applications., where memory access is unpredictable.

The QDR consortium-defined quadruple data rate (QDR?) SRAM products are geared primarily to the networking and communication market. QDR? SRAMs allow access to any two memory locations on every clock cycle, and performance never depends on which memory location was accessed in the previous clock cycle. Hence, with QDR? SRAM, RTR is guaranteed.

QDR?-IV SRAMs are capable of operating in burst-of-two or banked burst-of-two modes, which deliver the fastest clock speeds and highest RTR of all QDR? SRAMs and also higher than competing RLDRAMs and DDR3 DRAMs.

Infineon's QDR?-IV SRAMs provide RTRs up to 2132 MT/s.

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