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EZ-PD? CCG3PA Automotive USB-C and Power Delivery controller

Highly integrated USB-C Power Delivery solution supporting USB PD 3.1 and PPS mode for automotive charger ports

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Overview

EZ-PD? CCG3PA Automotive is a USB-C and Power Delivery controller targeted at in-vehicle charger ports. It supports Power Delivery 3.1 with programmable power supply (PPS) and integrates VBUS-to-CC short protection, 30 V-tolerant regulator, high-voltage PFET gate drivers, VBUS overvoltage and overcurrent protection, and ESD protection.

Key Features

  • Supports USB PD 3.1 v1.1 & PPS mode
  • Configurable resistors Rp and Rd
  • Supports one USB-C and USB-A port
  • Supports QC 4.0, 2.4A, AFC & BC 1.2
  • VBUS-to-CC short protection
  • VBUS, OVP, OCP, UVP, and SCP
  • 32-bit Arm? Cortex?-M0
  • System-level ESD protection
  • Automotive temperature range

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About

EZ-PD? CCG3PA Automotive integrates a 32-bit Arm? Cortex?-M0 CPU, specifically optimized to operate efficiently in low-power scenarios through the implementation of extensive clock gating techniques. The MCU includes a serial wire debug (SWD) interface, which serves as a two-wire variant of JTAG, enabling debugging capabilities. In terms of memory, the devices are equipped with a flash module featuring a single bank of 64 KB flash memory. To enhance the average access times from the flash block, a flash accelerator is tightly coupled to the CPU. Moreover, a supervisory ROM is provided, containing essential boot and configuration routines.

The USB PD subsystem provides the interface to the Type-C USB port. This subsystem comprises a current sense amplifier, a high-voltage regulator, overvoltage protection (OVP), overcurrent protection (OCP), and supply switch blocks. Additionally, this subsystem also includes all ESD protection required and supported on the Type-C port. The USB PD physical layer consists of both a transmitter and a receiver. These components facilitate the communication of BMC-encoded data over the CC channel, adhering to the PD 3.0 standard. All communication is half-duplex. To minimize communication errors, the physical layer (PHY) implements collision-avoidance techniques. The USB PD block incorporates all termination resistors (Rp and Rd) and their respective switches as mandated by the USB PD specification. As a car charger, EZ-PD? CCG3PA Automotive devices are in a DFP role (as a power source), which requires both CC lines to be open.

  • Dynamic load sharing between ports
  • Single-chip solution for systems with USB Type-C plus Type-A
  • Smart communication to media hubs in head units
  • Support for alternate modes (DisplayPort) for rear seat entertainment systems
  • Cable compensation to account for designs with pigtails
  • Smart power management with thermal- and VIN-based power throttling
  • Programmability enabling customization such as port priority, LED controls, etc.
  • Flash upgradability to keep up with the latest USB Power Delivery standards

EZ-PD? CCG3PA Automotive integrates a 32-bit Arm? Cortex?-M0 CPU, specifically optimized to operate efficiently in low-power scenarios through the implementation of extensive clock gating techniques. The MCU includes a serial wire debug (SWD) interface, which serves as a two-wire variant of JTAG, enabling debugging capabilities. In terms of memory, the devices are equipped with a flash module featuring a single bank of 64 KB flash memory. To enhance the average access times from the flash block, a flash accelerator is tightly coupled to the CPU. Moreover, a supervisory ROM is provided, containing essential boot and configuration routines.

The USB PD subsystem provides the interface to the Type-C USB port. This subsystem comprises a current sense amplifier, a high-voltage regulator, overvoltage protection (OVP), overcurrent protection (OCP), and supply switch blocks. Additionally, this subsystem also includes all ESD protection required and supported on the Type-C port. The USB PD physical layer consists of both a transmitter and a receiver. These components facilitate the communication of BMC-encoded data over the CC channel, adhering to the PD 3.0 standard. All communication is half-duplex. To minimize communication errors, the physical layer (PHY) implements collision-avoidance techniques. The USB PD block incorporates all termination resistors (Rp and Rd) and their respective switches as mandated by the USB PD specification. As a car charger, EZ-PD? CCG3PA Automotive devices are in a DFP role (as a power source), which requires both CC lines to be open.

  • Dynamic load sharing between ports
  • Single-chip solution for systems with USB Type-C plus Type-A
  • Smart communication to media hubs in head units
  • Support for alternate modes (DisplayPort) for rear seat entertainment systems
  • Cable compensation to account for designs with pigtails
  • Smart power management with thermal- and VIN-based power throttling
  • Programmability enabling customization such as port priority, LED controls, etc.
  • Flash upgradability to keep up with the latest USB Power Delivery standards

Design resources

Developer community

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