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D-DPAK and Q-DPAK

CoolMOS? SJ MOSETs and CoolSiC? Schottky diode Gen6 in double and quadruple DPAK (D-DPAK/Q-DPAK)

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Overview

With the D-DPAK package, Infineon introduced the first top-side cooled surface mount device (SMD) package addressing high-power SMPS applications such as PC power, solar, server, and telecom. With the latest Q-DPAK package, Infineon extended the top-side cooling offering even further. The Q-DPAK package is twice as big as the D-DPAK and extends the usage into higher power applications.?

Key Features

  • >20% higher power dissipation
  • >12¡ãC lower board temperature
  • Kelvin source pin
  • TCOB capability of >2000 cycles
  • MSL1-compliant
  • Pb-free

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About

CoolMOS??SJ MOSFET and CoolSiC??Schottky diode in D-DPAK/Q-DPAK package

Top-side cooled packages continue gaining market share, particularly in applications combining high-power handling requirements with converter size constraints. These top-side cooled packages respond to such requirements by separating the current distribution in the commutation loop (bottom/PCB side) from the path that transports the heat away from the die junction (top side). The results are a switching cell with exceptionally low parasitics (<5 nH) and best/lowest thermal resistance.

Latest generation double and quadruple DPAK MOSFET packages

The top-side cooling packages are very well received by the power electronic community - these packages offer performances (electric and thermal) unattainable with other packages (neither SMD or TH) and reduce the manufacturing costs through automated placement. Q-DPAK is now part of the JEDEC standard, facilitating dual sourcing.

Higher power density and system life with greater power dissipation

D-PAK and Q-DPAK provide a heat extraction through the top side of the component - thus only parasitic heat flux goes though the PCB. Higher power dissipation is therefore possible while the PCB runs cooler. The parasitic switching cell can now be routed optimally to >5 nH as the heat extraction no longer interferes with the distribution of current, allowing for faster commutation of larger currents.

CoolMOS??SJ MOSFET and CoolSiC??Schottky diode in D-DPAK/Q-DPAK package

Top-side cooled packages continue gaining market share, particularly in applications combining high-power handling requirements with converter size constraints. These top-side cooled packages respond to such requirements by separating the current distribution in the commutation loop (bottom/PCB side) from the path that transports the heat away from the die junction (top side). The results are a switching cell with exceptionally low parasitics (<5 nH) and best/lowest thermal resistance.

Latest generation double and quadruple DPAK MOSFET packages

The top-side cooling packages are very well received by the power electronic community - these packages offer performances (electric and thermal) unattainable with other packages (neither SMD or TH) and reduce the manufacturing costs through automated placement. Q-DPAK is now part of the JEDEC standard, facilitating dual sourcing.

Higher power density and system life with greater power dissipation

D-PAK and Q-DPAK provide a heat extraction through the top side of the component - thus only parasitic heat flux goes though the PCB. Higher power dissipation is therefore possible while the PCB runs cooler. The parasitic switching cell can now be routed optimally to >5 nH as the heat extraction no longer interferes with the distribution of current, allowing for faster commutation of larger currents.

Documents

Documents

Design resources

Developer community

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