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TriCore? uses a RISC-like register model and load/store architecture to support HLL (High-Level Language) compilers and their optimization strategies.

Fast context switching and low interrupt latencies mean that processor performance can be distributed flexibly among simultaneous tasks and peripheral events can be effectively controlled. Additionally, integrated debug hardware eases the software development cycle.

The TriCore? architecture can automatically save or store half the register context upon an interrupt within two cycles. This provides fast interrupt response times without the need for major upkeep before entering the real interrupt service routine. The ISA is also capable of interacting with different system architectures, including multiprocessing.

This flexibility allows different trade-offs between performance and cost at any time. The architecture¡¯s native microcontroller-DSP capabilities allow each TriCore? core¡¯s performance to be tuned by external software.

For example, the performance of a 300-MHz TriCore?-1.3 core with a sustained 450MIPS rating is 280 microcontroller MIPS + 170 DSP MIPS (or 200 microcontroller MIPS + 250 DSP MIPS), depending on the load-sharing implementation in the software.

Infineon¡¯s TriCore? architecture offers a flexible set of instruction formats to optimize code space. Although the architecture is 32-bit, there are also 16-bit instruction formats available. This helps you code the most frequently required instructions in a reduced amount of memory space, reducing the instruction code space by at least 33%, compared to conventional RISC architectures.

These are the key features of TriCore? architecture:

• 4 GB of address space
• 16-/32-bit instructions for reduced code size
• Branch instructions (using branch prediction)
• Low interrupt latency with fast automatic content switch using wide pathway to on-chip memory
• Zero overhead loop capabilities
• Dual, single-clock-cycle, 16x 16-bit multiply-accumulate unit (with optional saturation)
• Optional Floating-Point Unit (FPU) and Memory Management Unit (MMU)
• Extensive bit-handling capabilities
• Single Instruction Multiple Data (SIMD) packed data operations (2x 16-bit or 4x 8-bit operands)
• Flexible interrupt prioritization scheme
• Byte and bit addressing
• Memory protection and debug support

Thanks to its high real-time performance and embedded safety and security features, the TriCore? architecture is ideal for a wide range of embedded and automotive applications. These include:

• Computer Peripherals
• Automotive Powertrain Controllers
• Vehicle Dynamics Systems
• Wireless Communications
• Networking Equipment

An increasing number of embedded designs employ both a microcontroller or microprocessor and a DSP or hard-wired ASIC, but a single TriCore? device can replace both components to save you time and money. This is because TriCore? technology has inherent microcontroller-DSP capabilities and can switch between those tasks in a flash.

The single core of a TriCore? chip offers virtual multiprocessing capabilities, eliminating the need for multiple controllers and DSPs. On-chip memories enhance performance and reduce system power dissipation, while integrated system peripherals and customer-specific logic increase the overall system performance at a reduced cost.

This single-core design is vital for embedded systems, as more and more applications demand higher system performance at a reasonable price. With cost-effective processor performance, more work can be offloaded from hardware to software tasks running on these powerful, multi-tasking CPUs.

In 1999, we launched the first generation of the AUtomotive unifieD processOr (AUDO) family. Based on a combined RISC + MCU + DSP processor core, these 32-bit TriCore? microcontrollers were a computational revelation. We have been evolving and optimizing this concept ever since. Here are some of the standout generations of TriCore? chips:

• AURIX? TC2xx: A key example of the TriCore? success story lies with the AURIX? TC2xx multicore family. AURIX? combines functional safety support, strong performance, and a futureproof security solution in a highly scalable product family.

• AURIX? TC3xx: The AURIX? TC3xx family is manufactured in 40 nm embedded flash technology and designed for ultimate reliability in harsh automotive environments. Like other AURIX? MCUs, the dual frontend concept ensures continuous supply. It¡¯s supported by an extensive ecosystem that includes AUTOSAR libraries and safety software to help manufacturers meet SIL/ASIL safety standards.

• AURIX? TC4x: The scalable microcontroller TC4x family is the next generation on from Infineon¡¯s hugely popular AURIX? TC3x family. Its performance is boosted by the next-generation TriCore? 1.8 and the scalable AURIX? accelerator suite, including the PPU (Parallel Processing Unit) and multiple smart accelerators. With support for high-speed communication interfaces like 5G-bit Ethernet and PCIe and other interfaces like CAN-XL and 10BASE T1S Ethernet, you¡¯ll get the performance and flexibility you need to implement new automotive-specific microcontrollers with E/E architectures.

The scalable family concept of TriCore? AURIX? chips facilitates a common software architecture. This helps you save significant money on platform software and gives you plenty of headroom to grow your business.

Combining the power of a microcontroller, a DSP, and a RISC processor into one single core, TriCore? chips are the future of technology. They¡¯re ideal for a wide range of industrial and automotive applications, including computers, networking, communications, and manufacturing. To secure your business¡¯s future and guarantee scalability, shop our range of products today.